1. Field of the Invention
The present invention relates to a semiconductor integrated circuit, and more particularly to the layout of peripheral circuits which are connected to an address bus.
2. Description of the Related Art
A system large scale integrated circuit (a system LSI) is known as a conventional semiconductor integrated circuit. In a system LSI, a plurality of peripheral circuits are electrically connected to a central processing unit (CPU) through a common address bus, so as to reduce a layout area of the bus configuration in the system LSI.
In a common address bus configuration, an address signal is communicated to both an accessed peripheral circuit and non-accessed peripheral circuits. As a result, a current flows in a circuit portion of the non-accessed peripheral circuits, for example, a write resister and a read resister. Accordingly, unnecessary power consumption occurs in the non-accessed circuits.
Recently, with the enhancement of the integration level of the system LSI, the number of the peripheral circuits included in the system LSI has increased, and accordingly, the unnecessary power consumption of the non-accessed peripheral circuits has increased. Further, since the number of the peripheral circuits has increased, it is desired to reduce the layout area of the address bus on the system LSI.